The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device having a resistor pair and applicable to semiconductor devices such as a bipolar static random access memory (RAM).
FIGS. 1 and 2 respectively show cross sections of examples of the conventional load resistance type bipolar static RAM. FIG. 3 shows a plan view of the conventional load resistance type bipolar static RAMs shown in FIGS. 1 and 2, and FIG. 4 shows a circuit diagram of these conventional load resistance type bipolar static RAMs. In FIG. 4, WL denotes a word line, and HL denotes a hold line.
In FIGS. 1 and 2, n.sup.+ -type buried layer 11 is formed in a p-type substrate 10, and an n-type layer 12 is formed on the n.sup.+ -type buried layer 11. A polysilicon layer 14 is provided above the n-type layer 12 via an insulator oxide layer 31. An insulator layer 32 is provided as shown.
The polysilicon layer 14 is divided into low resistance diffusion portions 14a and 14b, and a high resistance diffusion part 14c. The low resistance diffusion portions 14a and 14b are respectively provided within masks surrounded by dotted lines A1 and A2 in FIG. 3, and p-type impurities are diffused within these low resistance diffusion portions 14a and 14b at a low impurity concentration. The high resistance diffusion part 14c is provided within a mask surrounded by a dotted line A3 in FIG. 3, and p-type impurities are diffused within this high resistance diffusion part 14c at a high impurity concentration. A word line electrode W1 is formed on the low resistance diffusion part 14a. A base electrode B1, an n-type layer 15 which becomes an emitter for holding, an emitter electrode EH1, an n-type layer 16 which becomes an emitter for sensing, and an emitter electrode ES1 are formed on the low resistance diffusion part 14b. The high resistance diffusion part 14c is used as a load resistor R1. A collector C1 is formed on the n-type layer 12. In FIG. 1, a p-type isolation 17 is provided around the n-type layer 12. In FIG. 2, an isolation 17 formed by an insulator is provided around the n-type layer 12.
The sheet resistance ratio between the low resistance diffusion part 14a or 14b and the high resistance diffusion part 14c is in the range of 1:50 to 1:100, and the actual resistance of the load resistor R1 is determined by the high resistance diffusion part 14c. The resistance of the load resistor R1 can be described by the following formula, where L denotes a low resistance diffusion interval L in FIG. 5 which shows a partially enlarged plan view, W denotes a polysilicon width W in FIG. 5, .sigma. denotes a sheet resistance, and R1 denotes the resistance of the load resistor R1. EQU R1=.sigma..multidot.L/W
In FIG. 5, when an alignment error between a mask which forms the polysilicon layer 14 and a mask which forms the isolation 17 is taken into consideration, no problem will occur for the alignment error in a direction X but a problem will occur for the alignment error in a direction Y.
In other words, if the mask which forms the polysilicon layer 14 shifts downwards in FIG. 5, the polysilicon layer 14 will partially overlap the isolation 17. In this case, the polysilicon width W becomes narrow and the actual resistance of the load resistor R1 becomes large. On the other hand, with regard to a load resistor R2 on the opposite side from the load resistor R1 and forming a flip-flop of a memory cell, the polysilicon layer shifts in a direction so as to separate from the isolation, and the actual resistance of the load resistor R2 will not change.
In the case where the load resistor R1 is formed as a thin film resistor by forming the polysilicon layer 14 on the substrate 10, the portion of the polysilicon layer 14 overlapping the stepped or sloping portion of the isolation 17 becomes thinner compared to other portions of the polysilicon layer 14. It is for this reason that the polysilicon width W substantially becomes narrow and the actual resistance of the load resistor R1 becomes large.
On the other hand, in the case where the load resistor R1 is formed by ion implantation into the substrate 10, the injected ions landing on the isolation 17 will not form a resistor at the isolation 17. In other words, only the diffused or doped region of the substrate 10 becomes the load resistor R1. It is for this reason that the resistor width substantially becomes narrow and the actual resistance of the load resistor R1 becomes large.
For example, when the resistances of the pair of load resistors R1 and R2 of the flip-flop forming the memory cell becomes unbalanced, there was a problem in that the soft error which is the inverse number of the probability of an erroneous operation occurring due to the a-ray becomes unbalanced between the case where the memory cell holds a logic value "1" and the case where the memory cell holds a logic value "0".
Furthermore, problems occurred where a resistor pair needed to have balanced resistances in order for the semiconductor device to carry out the designed operations.